Funding Opportunity: NSTC Scalable Memory Architecture Program NOTE: PROPOSER'S DAY: Apr. 29 DUE DATE

The National Center for the Advancement of Semiconductor Technology (Natcast), the operator of the National Semiconductor Technology Center (NSTC) consortium, has issued a fourth microelectronics research and development (R&D) program, Scalable Memory Architecture Program (SMAP). The goal of SMAP is to address the “memory wall” or increasing difference between processor speed and memory bandwidth.

Background: SMAP aims to develop new architectural solutions that leverage new memory technologies and advanced packaging techniques to create the “data, tools, and technology assessment capabilities needed to optimize performance, reduce latency, and improve energy efficiency in high computing data center systems and energy-constrained edge systems.” SMAP will fund research teams in two focus areas: data center compute systems, and edge compute systems. Within each focus area, the teams will cover three technology areas: new memory technologies, advanced packaging technologies, and programming models.

Additional information will be included in the call for proposals to be issued on April 14, 2025.

Funding: Natcast is allocating up to $33.5 million in total funding for this topic and anticipates making 8-14 awards, ranging from $2 to $5 million each for up to 30 months. To submit proposals, applicants must be eligible to become NSTC members and are required to be NSTC members at the time of the award. Domestic for-profit organizations, non-profit organizations, and accredited institutions of higher education are all eligible to apply.

Key Dates: The full call for proposals is expected to be issued on April 14, 2025; the SMAP proposers’ day (in-person and virtual option) will be held in Columbus, OH on April 29, 2025; concept papers are due May 6, 2025; full proposals are due June 17, 2025; and projects should start in December 2025.

Previous NSTC R&D topics include Artificial Intelligence Driven Radio Frequency for Integrated Circuits (AIDRFIC); Test Vehicle Innovation Pipeline (TVIP); and Polyfluoroalkyl Substances Reduction and Innovation in Semiconductor Manufacturing (PRISM). Lewis-Burke will continue to monitor and share NSTC's forthcoming activities.

Sources and Additional Information:

Source: Lewis-Burke Associates, LLC, April, 2025

Contact info

Julie O'Connor

Director, Research Communications
Phone: 313-577-8845
Email: julie.oconnor@wayne.edu